Silicon Design Engineer
Core
Lead and contribute to the design, integration, verification, and characterization of advanced silicon testchips supporting FPGA and ASIC products on leading-edge process technologies.
Role type
Senior IC silicon design engineer (physical design)
Builds
Digital ASIC/SoC chips for FPGA and ASIC products
Domain
Semiconductor hardware design (ASIC/SoC)
Required skills
RTL-to-GDS implementation, physical design flow (floorplanning, placement, CTS, routing), Static Timing Analysis (STA), physical signoff (DRC/LVS, IR drop, EM, noise), tapeout readiness, post-silicon validation, Python/Tcl scripting
Preferred skills
CMOS circuit design fundamentals, semiconductor device physics, FinFET/GAA node experience, lab-based validation, complex design debugging
Technologies
Design Compiler, PrimeTime, Cadence Genus/Innovus, Synopsys Fusion Compiler
Responsibilities
Drive timing-aware/physical-aware synthesis flow, lead end-to-end digital ASIC/SoC physical design cycle, close SoC timing with STA, perform physical signoff analyses, develop verification plans and testbenches, assist with post-silicon bring-up and debugging
Seniority
Senior, hands-on IC
