Sr. ASIC Design Engineer (Silicon Engineering)
Core
Developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity.
Role type
Senior IC ASIC Design Engineer
Builds
Next-generation ASICs for Starlink satellites and ground infrastructure
Domain
Aerospace / Satellite Communications / Silicon Design
Required skills
RTL implementation (Verilog/System Verilog), micro-architecture definition, timing closure, silicon bring-up, clock domain crossing, power optimization, embedded CPU subsystems, standard bus protocols (AXI, AHB), EDA tools, Python scripting
Preferred skills
ASIC/SoC system integration, high-speed design techniques
Responsibilities
Evaluate architectural trade-offs, define micro-architecture and implement RTL, integrate designs at top level, collaborate with verification teams, provide timing constraints for IPs, participate in silicon bring-up and validation
Seniority
Senior, hands-on IC
