Senior DFT Design Engineer (ATPG/Scan stitching)
Core
Implement and verify DFT features (SCAN, MBIST, LBIST, JTAG), generate ATPG patterns, and support post-silicon bring-up to enhance yield.
Role type
Senior DFT Design Engineer (ATPG/Scan stitching)
Builds
High-quality semiconductor chips for AI, data centers, PCs, gaming, and embedded systems
Domain
Semiconductor / Digital Design / Test Engineering
Required skills
Scan insertion, ATPG pattern generation, MBIST/BISR implementation, JTAG basics, Spyglass-DFT debug, gate-level simulation, test coverage analysis, scripting (TCL/AWK/SED)
Preferred skills
Scan-stitching concepts, Tessent flow (MBIST/ATPG), post-silicon bring-up experience
Technologies
Spyglass-DFT, Tessent, Mentor ATPG, TCL, AWK, SED
Responsibilities
Implement and verify DFT features like SCAN, MBIST, LBIST and JTAG; Support Spyglass-DFTDRC debug and coverage correlation; Perform scan insertion and ATPG pattern generation; Verify ATPG patterns with gate-level simulation; Conduct test coverage and test cost reduction analysis; Provide post silicon support for bring up and yield learning
Seniority
Senior, hands-on IC
