Lead STA / Timing analysis Design Engineer
Core
Develop complex multi-mode/multi-corner timing constraints for RTL and signoff, drive timing closure for sub-chips/subsystems or full chips, and generate timing ECOs.
Role type
Senior IC silicon design engineer (STA/Timing)
Builds
High-frequency digital logic blocks, subsystems, and full-chip implementations for AI, data centers, PCs, gaming, and embedded systems.
Domain
Semiconductor hardware design, Static Timing Analysis (STA), Physical Design
Required skills
SDC constraint development, timing signoff methodology, Tcl scripting, timing report analysis, DFT mode requirements, physical design flow, ECO implementation, OCV/AOCV/POCV analysis
Preferred skills
High-frequency timing closure (> GHz), Synopsys tools (Design Compiler, Primetime, Fishtail, Tweaker), Spyglass
Technologies
Synopsys Design Compiler, Synopsys Primetime, Fishtail, GCA, Spyglass, DMSA, Tweaker, Tcl, Linux
Responsibilities
Develop multi-mode/multi-corner timing constraints compatible with RTL and signoff; Ensure constraints quality (SDC) using industry tools; Drive pre-route timing checks and QoR cleanup; Perform timing closure for sub-chips, subsystems, or full chips; Generate timing ECOs using DMSA/Tweaker.
Seniority
Senior, hands-on IC
