Staff DFx Methodology Architect
Core
Define and lead SoC-DFx Architecture, Specifications, and development of DFx-IPs for FPGA-SoCs and custom ASICs, ensuring Power, Performance, and Area (PPA) optimization.
Role type
Staff DFx Methodology Architect (IC)
Builds
DFx-IPs, SoC-DFx Architecture, and Design Methodologies for next-generation computing products
Domain
Semiconductor / Hardware Design / Digital Logic
Required skills
RTL design (Verilog/SystemVerilog), DFT Architecture, Timing analysis, Logic design, Switching theory, Silicon debug, Cross-functional negotiation, Mentorship
Preferred skills
Siemens Tessent DFT flows, ATPG, 2.5D/3D IC testing, Scripting (Perl/Python/TCL), Leadership experience
Technologies
Verilog, SystemVerilog, Siemens Tessent, Perl, Python, TCL
Responsibilities
Define SoC-DFx Architecture and specifications; Implement DFx features in RTL; Co-own Timing and Design Quality Checks; Collaborate with verification and validation teams on test plans and silicon bring-up; Contribute to front-end and timing methodologies.
Seniority
Staff, hands-on IC with mentorship
