IP/Subsystem Verification Lead
Core
Lead verification efforts for complex RTL blocks and SOCs destined for next-generation Data Center networking ASICs.
Role type
Principal Design Verification Engineer (IC)
Builds
RTL blocks, subsystems, and SOCs for AI NICs, low latency/high speed NICs, and GPU cluster networking.
Domain
Semiconductor / VLSI / Data Center Networking
Required skills
UVM-based verification, SystemVerilog, simulation-based verification, verification coverage closure, technical leadership
Preferred skills
Synopsys functional verification tools, full chip verification, formal verification, AI-based debug techniques, Python, C/C++, RTL design, networking technologies
Technologies
SystemVerilog, UVM, Synopsys tools, Python, C/C++
Responsibilities
Lead verification teams, execute simulation-based verification for ASIC/FPGA blocks, achieve verification coverage closure
Seniority
Principal, hands-on IC
