Sr. System RTL Designer/Serdes Architect
Core
Define IP features and capabilities, own architecture and micro-architecture requirements, and drive technical specifications for IP blocks to deliver groundbreaking silicon solutions.
Role type
Senior System RTL Designer / SerDes Architect
Builds
CPU/GPU/SoC silicon solutions
Domain
Semiconductor hardware design (SerDes, fabrics, memory subsystems, I/O, clocking)
Required skills
System and IP architecture, SerDes, fabrics, memory subsystems, I/O, clocking, security, CPU/GPU system-level performance analysis, power management, low power microarchitecture, design methodologies
Preferred skills
Cross-functional collaboration, communication, stakeholder influence
Technologies
RTL, SerDes, fabrics, memory subsystems, I/O, clocking
Responsibilities
Define IP features and capabilities; own architecture and micro-architecture requirements; Drive technical specifications for IP blocks and provide direction to execution teams; Align and optimize hardware (silicon), firmware, and feature enablement for performance and power; Collaborate cross-functionally to identify risks and resolve architecture-level issues; Own architecture analysis and support feature-change requests from marketing/business teams; Partner with design teams on area/floorplan refinement, timing targets, verification test plans, and pre-silicon debug/performance sign-off; Support post-silicon teams for performance tuning, power optimization, and issue debug
Seniority
Senior, hands-on IC
