Lead IP Block level Verification Engineer
Core
Lead verification of Network on Chip (NOC) IPs and subsystems using simulation and formal methods to prove functional correctness.
Role type
Senior IC verification engineer (NOC/SOC)
Builds
Network-on-Chip (NOC) IPs, subsystems, and SOC designs
Domain
Semiconductor / VLSI / ASIC
Required skills
System Verilog, UVM, constrained-random verification, formal verification (SVA), coverage analysis, testbench architecture, debug, testplan creation
Preferred skills
NOC verification, AXI/PCIe/DDR protocols, gate-level simulation, power verification, formal property checking tools (Jasper, VC-Formal)
Technologies
System Verilog, UVM, Synopsys VCS, Cadence IES, Jasper, VC-Formal, Magellan, SVA
Responsibilities
Lead and plan verification of complex digital design blocks; Interact with architects to create verification testplans; Design and architect testbenches in System Verilog and UVM; Create constrained-random and formal verification environments; Debug tests with design engineers; Perform coverage analysis to achieve closure
Seniority
Senior, hands-on IC
