Senior Staff Engineer Chip Package Board - CoDesign Flow and Methodology (f/m/div)
Core
Define and drive the technical roadmap for Chip-Package-Board (CPB) design methodologies, flows, tools, and digital engineering capabilities to accelerate design convergence and improve quality.
Role type
Senior Staff Engineer, CPB CoDesign Flow and Methodology
Builds
Scalable, reusable, and sustainable methodology solutions, standards, and governance models across the CPB ecosystem.
Domain
Semiconductor industry, advanced packaging, heterogeneous integration, System-in-Package (SiP), 3D design.
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor product development, EDA environments, package development, design automation, simulation, strategic thinking, cross-functional leadership, technology roadmap definition.
Preferred skills
AI-enabled engineering workflows, data-driven engineering concepts, software development, digitalization initiatives.
Technologies
Cadence, Synopsys, Keysight, Comsol.
Responsibilities
Define and drive the technical roadmap for CPB design methodologies and flows; Translate Business Line needs into methodology enhancements and EDA roadmap requirements; Drive continuous improvement of CPB methodologies and engineering workflows; Identify and shape future capabilities for advanced packaging and AI-assisted workflows; Lead AI, automation, and digitalization initiatives; Provide technical leadership, consulting, and training for global user communities.
Seniority
Senior Staff, hands-on IC with strategic leadership
