Pre‑Silicon Power Modeling Leader — x86 SoCs
Core
Lead SoC-level pre-silicon power modeling to deliver accurate Perf/Watt projections, robust DVFS/AVFS plans, and silicon correlation for x86 SoCs.
Role type
Senior IC power modeling engineer (x86 SoC)
Builds
Pre-silicon power models, DVFS/AVFS strategies, and correlation reports for x86 SoCs
Domain
Semiconductor hardware design (x86 SoC power modeling)
Deliverable
production ML models
Required skills
SoC power modeling, EDA tooling (PowerArtist, PrimeTime PX), x86 micro-architecture, DVFS/AVFS strategy, Python automation, UPF/CPF power intent, activity annotation (FSDB/VCD), IP-level VBM integration, workload-based projections, power delivery/PDN interactions, EDC/TDC/CaC semantics
Preferred skills
Automotive power modeling (AEC-Q100/ASIL), system performance modeling (GEM5/Simics/SystemC), PnP dashboards (Python/Jenkins/Grafana/InfluxDB)
Technologies
PowerArtist, PrimeTime PX, Python, FSDB, VCD, UPF, CPF, GEM5, Simics, SystemC, Jenkins, Grafana, InfluxDB
Responsibilities
Own the SoC power model end-to-end using AMD's converged methodology; define use-case power envelopes across automotive, networking, storage, industrial, and robotics segments; drive DVFS/AVFS strategy and telemetry requirements; establish IP/subsystem power budgets and run sensitivity studies; build repeatable model-to-silicon correlation plans; lead tool flows & automation for activity ingestion and report generation; collaborate across Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP
Seniority
Senior, hands-on IC
