AI芯片互联设计工程师 - 芯片研发
Core
Designing AI chip interconnect solutions and ASIC micro-architecture for cloud and edge AI scenarios.
Role type
Senior IC ASIC design engineer (AI interconnect)
Builds
High-performance AI chips and SoCs for inference and training
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
ASIC micro-architecture design, RTL development, Verilog, Scale Up/Scale Out protocols, Computer architecture, MAC/PCIe/AMBA interfaces
Preferred skills
AI training/inference parallelism strategies, GPU architecture, High-speed network networking, Congestion control, RDMA drivers, Collective communication software
Technologies
Verilog, MAC, PCIe, AMBA, RDMA, GPU
