Verification Engineer - Onsite PA or CA (6269)
Core
Develop and maintain UVM-based verification environments for ASIC/SoC designs, creating verification plans and components like assertions and agents.
Role type
Senior IC verification engineer (ASIC/SoC)
Builds
High-quality silicon solutions for next-generation System-on-Chip (SoC) designs
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, SystemVerilog, ASIC/SoC verification, verification planning, block/system-level verification, timing/gate-level simulation, C programming for firmware
Preferred skills
Formal verification, Python/Perl scripting, high-speed serial protocols (UCIe, PCIe), analog verification
Technologies
UVM, SystemVerilog, C, Python, Perl
Responsibilities
Develop and maintain UVM-based verification environments; Create and execute block- and system-level verification plans; Design verification components including assertions, agents, traffic generators, and scoreboards; Debug and resolve complex design and verification issues; Perform timing and gate-level simulations; Support post-silicon bring-up through C-based firmware development
Seniority
Senior, hands-on IC
