DPU验证工程师-Data（深圳）
Core
Build and maintain UVM verification environments for DPU chips, focusing on automated, reusable environments and high-quality delivery of code and functional coverage.
Role type
Senior IC verification engineer (DPU)
Builds
DPU chips
Domain
Semiconductor / Hardware verification / Data center networking
Required skills
UVM, System Verilog, Makefile, Perl, Python, C/C++, PCIe protocol, Ethernet protocol, RoCEv2/3, VirtIO, AXI4
Preferred skills
System-level networking, storage, NVMe, virtualization, SR-IOV, compression algorithms
Technologies
UVM, System Verilog, Makefile, Perl, Python, C/C++, PCIe, Ethernet, RoCEv2/3, VirtIO, AXI4, NVMe, SR-IOV
Responsibilities
Build UVM verification environments; Develop automated and reusable verification environments; Create verification plans and collect code/functional coverage; Execute performance verification, power-aware simulation, RTL/FW co-simulation, and GLS simulation; Analyze regression results and assist design engineers in debugging; Improve and refine verification processes.
