Design Verification Engineer
Core
Staff Design Verification Engineer developing leading-edge memory interface products for data center, AI, and cloud computing applications.
Role type
Staff IC design verification engineer
Builds
Advanced memory data buffer products including DDR6 and future generations
Domain
Semiconductor / Memory Interfaces / Data Center & AI
Required skills
SystemVerilog, UVM, verification planning, functional verification, coverage analysis, testbench development, debugging, block-level verification, system-level verification
Preferred skills
DDR4/DDR5 experience, high-speed memory interfaces, verification methodology improvement, mentoring
Technologies
SystemVerilog, UVM, DDR6, DDR5
Responsibilities
Drive verification activities for complex digital designs at block and system level; Develop and execute verification plans based on functional and performance specifications; Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches; Develop verification tests, functional coverage, checkers, and other verification components; Take ownership of verification environments and verification execution for assigned blocks and features; Drive and monitor coverage to ensure verification goals are achieved; Analyze verification results, debug failures, and identify functional or design issues; Identify and implement improvements to verification processes, methodologies, and design behavior; Serve as a technical resource within the team, providing guidance on complex verification problems and sharing best practices.
Seniority
Staff, hands-on IC with mentorship
