Principal Design Verification Engineer
Core
Provide technical leadership for verification of next-generation semiconductor memory interface products, including data buffer silicon.
Role type
Principal Design Verification Engineer (semiconductor)
Builds
Next-generation DDR6 memory interface silicon
Domain
Semiconductor / Memory Interfaces / Digital Design
Required skills
SystemVerilog, UVM, verification strategy, constrained-random verification, functional coverage, debugging, technical leadership, mentoring
Preferred skills
DDR memory experience, DDR4/DDR5, high-speed interfaces, mixed-signal verification
Technologies
SystemVerilog, UVM, DDR6, DDR4, DDR5
Responsibilities
Lead verification strategy and execution for complex semiconductor designs; Define verification methodologies, test plans, and coverage strategies; Architect and optimize SystemVerilog/UVM testbenches; Drive test development and coverage closure; Provide technical guidance and mentorship to verification engineers; Analyze specifications and results to identify functional gaps; Communicate verification progress and risks to stakeholders.
