Principal/Lead Digital RTL Design Engineer (Power Management ICs)
Core
Develop, debug, and verify digital designs for advanced power management ICs in pre and post silicon environments.
Role type
Principal/Lead Digital RTL Design Engineer (Power Management ICs)
Builds
Industry leading digital power management ICs
Domain
Semiconductor / Power Management ICs
Required skills
Verilog, System Verilog, CDC/RDC/LINT debugging, gate level simulation, serial interfaces (I2C, I3C, SPI, I2S), Cadence/Synopsys flows, design automation scripting, technical mentorship
Preferred skills
Python/Perl scripting, ARM Cortex M-series architecture, mixed-signal design basics, digital backend flow (synthesis/STA/P&R), PMBus/SMBus/AVSBus/SVID/SVI3
Responsibilities
Develop and verify digital designs; write verification tests; develop design automation scripts; manage design blocks; research new tools; mentor junior engineers; lead digital design in projects
Seniority
Principal, hands-on IC with technical leadership
