Senior Analog Engineering Manager
Core
Lead the architecture, design, and implementation of DDR5 and DDR6 PHYs for high-speed memory interfaces in advanced SoCs.
Role type
Senior Analog Engineering Manager (High-Speed Memory Interfaces)
Builds
High-performance, low-power DDR5/DDR6 PHYs for automotive, industrial, infrastructure, and IoT applications
Domain
Semiconductor / High-Speed Memory Interfaces / Analog & Mixed-Signal IC Design
Deliverable
production ML models | product features
Required skills
Analog/mixed-signal IC design, High-speed IO design and signal integrity, PLL/DLL and low-jitter clocking architectures, Mixed-signal verification and silicon validation, Advanced CMOS process considerations, Timing closure (jitter, noise, SI/PI), PVT robustness, JEDEC DDR5/DDR6 standards compliance, Post-silicon bring-up and debug, Team leadership and hiring, Cross-functional program execution
Preferred skills
DDR6 architectural studies, Experience at 7nm/5nm nodes, Multi-generation memory PHY platforms, Leading concurrent tape-outs
Technologies
DDR5, DDR6, PLL, DLL, CMOS, SoC, JEDEC
Responsibilities
Own and guide architecture/design of DDR5 PHYs and contribute to DDR6-ready architectures; Provide technical oversight for analog/mixed-signal blocks (TX/RX datapaths, equalization, termination, clocking, power-aware IO); Drive closure on timing, jitter, noise, SI/PI, and PVT robustness; Lead post-silicon bring-up, characterization, debug, and yield improvement; Build, lead, and mentor a team of analog/mixed-signal designers; Own DDR5/DDR6 PHY execution balancing schedule, quality, and risk; Partner with digital PHY, SoC integration, package, PCB, SI/PI, validation, product, and program management teams; Establish robust design and signoff methodologies; Lead long-term DDR5 sustainment and DDR6 technology roadmap planning
Seniority
Senior, hands-on IC with people management
