ASIC Verification EEJ 2026
Core
Verification of SoCs, automotive ASICs, and subsystems using Metric-driven Verification (MDV) and Formal Verification methodologies.
Role type
Senior IC ASIC Verification Engineer
Builds
Automotive SoCs and ASICs
Domain
Automotive electronics / Digital IC design
Deliverable
production ML models | product features
Required skills
System Verilog, UVM, constrained random verification, functional coverage development, regression analysis, AMBA protocols, ARM processor-based SoC verification, EDA tool usage (Cadence/Synopsys/Mentor), scripting (Perl/TCL), configuration management
Preferred skills
Formal verification, VIP development, VHDL/VERILOG, SPECMAN
Technologies
System Verilog, UVM, Cadence, Synopsys, Mentor, Perl, TCL, AMBA, ARM
Responsibilities
Develop verification environments from scratch, create and track verification plans, integrate VIPs, measure and analyze regression results, apply MDV and Formal Verification methodologies, improve verification flows with EDA partners
Seniority
Senior, hands-on IC
