Staff/Sr Staff Engineer, Physical Design
Core
Lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes.
Role type
Senior Staff IC physical design engineer (subsystem/block level)
Builds
Subsystem and block-level physical implementations for complex hierarchical SoCs
Domain
Semiconductor / SoC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (physical implementation)
Required skills
Timing closure, congestion analysis and resolution, power integrity, clocking methodologies, block/subsystem physical design flows, SoC floorplanning, clock tree architecture, skew management, clock gating, Tcl/Python/Perl scripting, low-power design techniques
Preferred skills
Cross-functional collaboration with RTL/STA/power/verification teams, mentorship of physical design engineers, risk mitigation strategies
Technologies
Synopsys ICC2, Fusion Compiler, PrimeTime, Cadence Innovus, Tempus, Certus
Responsibilities
Lead block- and subsystem-level physical design closure, collaborate with SoC teams on clocking strategies and floorplanning, develop and scale closure methodologies and automation, mentor physical design engineers, work cross-functionally with RTL/STA/power/verification teams, identify and mitigate physical design risks
Seniority
Senior Staff, hands-on IC with mentorship
