Senior Principal Design Verification Engineer
Core
Lead verification efforts for Automotive PMIC (Power Management Integrated Circuit) product line, combining mixed-signal verification methodology with leadership to mentor engineers and drive strategy.
Role type
Senior Principal Design Verification Engineer (Mixed-Signal/Analog)
Builds
Automotive PMIC designs and power management systems
Domain
Automotive semiconductor / Mixed-signal verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Mixed-signal verification, Real Number Model (RNM), AMS model integration, Gate-Level Simulation (GLS), RTL simulation, analog block debugging (regulators, LDO, bandgap), Verilog, SystemVerilog, SPICE, UVM, coverage-driven verification, ISO 26262 compliance, AEC-Q200 compliance, cross-functional collaboration, technical mentoring
Preferred skills
AI-based verification solutions, emerging verification technologies, post-silicon validation, ATE test correlation
Technologies
Spectre, Xcelium, Verilog, SystemVerilog, SPICE
Responsibilities
Architect mixed-signal verification environments; develop verification plans for automotive PMIC; optimize GLS flows; lead debugging of analog blocks; conduct RTL and Gate-Level simulations; collaborate with Design, ATE, and Silicon Validation; mentor junior engineers; drive tool and methodology improvements; create verification documentation.
Seniority
Principal, hands-on IC with strategic leadership
