DMS Verification Engineer
Core
Develop and execute comprehensive verification strategies for state-of-the-art Mixed-Signal SoCs by collaborating with system architects and analog/digital designers.
Role type
Senior IC DMS Verification Engineer
Builds
Mixed-Signal SoCs
Domain
Semiconductor / Mixed-Signal SoC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, Verilog, UVM, Gate-Level Simulation (GLS), Root-cause analysis, Behavioral modeling, DSP techniques, Analog schematics
Preferred skills
Formal Verification, Python, Shell scripting
Technologies
Vmanager, UVM
Responsibilities
Drive specification reviews to generate initial verification plans; Define verification strategies including partitioning between DMS and DV; Plan and manage resources, schedules, and progress tracking; Implement verification plans, run regressions, and track coverage; Verify accuracy of behavioral models against circuit-level simulations; Perform root-cause analysis and debug issues down to RTL, gate, and schematic levels; Maintain and improve functional verification infrastructure and flows.
Seniority
Senior, hands-on IC with mentorship responsibilities
