Senior Principal Verification Engineer
Core
Architect mixed-signal verification environments and lead verification strategy for automotive PMIC designs, ensuring compliance with safety standards.
Role type
Senior Principal Verification Engineer (Mixed-Signal/Analog)
Builds
Automotive Power Management Integrated Circuits (PMIC)
Domain
Automotive semiconductor / Analog Mixed-Signal
Deliverable
production ML models | product features
Required skills
Mixed-signal verification architecture, Real Number Model (RNM) integration, AMS model integration, Gate-Level Simulation (GLS) setup and debugging, RTL and behavioral simulation, analog block debugging (regulators, LDO, bandgap), Verilog/SystemVerilog/SPICE, UVM, coverage-driven verification, cross-domain verification (functional, post-silicon, ATE), leadership and mentoring
Preferred skills
Experience with AI-based verification solutions, deep understanding of PVT corners
Technologies
Spectre, Xcelium, UVM, SystemVerilog, Verilog, SPICE
Responsibilities
Design and architect mixed-signal verification environments; Develop and implement comprehensive verification plans and strategies; Set up and optimize Gate-Level Simulation (GLS) flows; Lead debugging activities for complex analog blocks; Conduct in-depth RTL and Gate-Level simulations; Collaborate with cross-functional teams (Design, ATE, Silicon Validation); Mentor and lead junior verification engineers; Drive continuous improvement of verification tools and methodologies; Create and maintain comprehensive verification documentation and coverage metrics
Seniority
Principal, hands-on IC with strategic leadership
