Principal Engineer- Digital Design
Core
Lead micro-architecture, design, and execution of next-generation UA Link Switch solutions for high-bandwidth, low-latency connectivity in AI, HPC, and memory-centric systems.
Role type
Principal Engineer / Senior Manager - Digital Design
Builds
High-speed switching fabrics and interconnect subsystems for silicon products
Domain
Semiconductor / High-speed digital design / SoC development
Deliverable
production ML models | product features
Required skills
High-speed digital design, SoC architecture and integration, Switching fabric design, Network-on-Chip (NoC), High-speed interconnects, Memory subsystem design, RTL design (Verilog/SystemVerilog), ASIC development flows (synthesis, STA, low-power), Silicon bring-up, Cross-functional technical leadership
Preferred skills
High-speed SerDes-based systems, Switching fabrics and packet processing architectures, Memory interface technologies, AI/HPC interconnect solutions, PCIe, CXL, Ethernet, UCIe, Large-scale SoC development for networking/compute/storage, System-level architecture and board-level considerations, Leading geographically distributed engineering teams
Technologies
Verilog, SystemVerilog, ASIC flows, SerDes, PCIe, CXL, Ethernet, UCIe
Responsibilities
Lead digital architecture and design activities for UA Link Switch products, Define and drive microarchitecture/RTL design/integration/performance optimization, Collaborate with architecture/verification/firmware/physical design/signal integrity/system teams, Drive end-to-end development from requirements to silicon bring-up, Provide technical leadership and mentor senior engineers, Analyze performance/power/area/scalability trade-offs, Participate in architectural reviews and roadmap planning
Seniority
Principal / Senior Manager, hands-on IC with strategic leadership
