Sr. Staff Digital Verification Engineer
Core
Design and develop verification environments for digital designs, ensuring functionality through simulations and regression testing.
Role type
Sr. Staff Digital Verification Engineer
Builds
RTL and gate-level simulation environments for embedded semiconductor products
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, RTL simulation, gate-level simulation, code coverage development, test plan creation, assertion writing, debugging designs, Python scripting, C/C++/Java, object-oriented programming, software design patterns, mixed signal verification, logic and circuit design basics
Preferred skills
Experience with verification environments over 10K lines, mixed signal verification, industry standard verification tools and flow, basic computer architecture knowledge
Technologies
SystemVerilog, UVM, Python, C, C++, Java
Responsibilities
Understand expected functionality of designs, design and develop verification environment, improve verification architecture and flow, run RTL and gate-level simulations/daily regression, code/functional coverage development, analysis and closure
Seniority
Sr. Staff, hands-on IC
