Sr Staff Design Verification Engineer
Core
Architecting and implementing verification environments for complex SoC designs in next-generation power management solutions.
Role type
Sr Staff Design Verification Engineer (SoC/Power Management)
Builds
Verification environments, agents, sequences, drivers, monitors, and scoreboards for automotive, industrial, infrastructure, and IoT SoCs.
Domain
Semiconductor / Embedded Systems / Power Management
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM methodology, SystemVerilog, Verilog, C/C++, Python, Perl, SoC architecture, Mixed-signal design, Analog components (ADC, DAC, PLL, Oscillators, PI controllers), Debugging RTL and Gate simulations, Regression systems, Revision control
Preferred skills
Directed and constrained random verification, Test pattern conversion, ATE vector bring up, Mentorship
Technologies
UVM, SystemVerilog, Verilog, C/C++, Python, Perl, Shell, Gate-level simulators, Regression systems
Responsibilities
Define verification plans, methodologies, and coverage strategies; Architect and implement verification environments from scratch; Lead end-to-end verification including gate-level simulations, coverage analysis, and closure; Mentor junior and mid-level verification engineers; Debug RTL and Gate simulations; Convert verification tests to test patterns.
Seniority
Sr Staff, hands-on IC with mentorship
