Senior FPGA Design Verification Engineer
Core
Verification of FPGA designs on daVinci robotic surgical systems to ensure RTL functional correctness from test planning to coverage closure.
Role type
Senior FPGA Design Verification Engineer
Builds
Verification environments and testbenches for robotic surgical hardware
Domain
Medical robotics / FPGA design
Deliverable
production ML models | product features
Required skills
UVM methodology, SystemVerilog, Verilog, constrained random testing, coverage modeling, Perl scripting, Python scripting, debugging, emulation/FPGA prototyping
Preferred skills
Formal verification, ML-assisted verification flows, agentic-AI automation frameworks
Technologies
UVM, SystemVerilog, Verilog, Perl, Python
Responsibilities
Develop testbenches using UVM, write constrained random stimulus, define coverage models, debug failures and analyze coverage metrics, collaborate with design teams on specifications and architecture
Seniority
Senior, hands-on IC
