Sr. Layout Engineer
Core
Designing mask layouts for next-generation LV and MV shielded-gate trench MOSFET technologies to optimize performance and accelerate product industrialization.
Role type
Senior IC layout engineer (power semiconductor)
Builds
Mask layouts for shielded-gate trench MOSFETs
Domain
Power semiconductor manufacturing
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Mask layout design, DRC verification, T/O procedure management, Scribe design, Alignment mark design, Inspection mark design, Shot map creation, Design rule compliance
Preferred skills
Process integration collaboration, Foundry partner coordination, Product industrialization
Technologies
Virtuoso, Calibre
Responsibilities
Chip layout design for LV/MV shield-gate trench MOSFETs, Verification of mask design rule check, Schedule adjustment and provenance tracking, Define mask specification, Scribe design and accessory layout, Build related documents including shot map
Seniority
Senior, hands-on IC