Sr Physical Design Engineer
Core
Execute full RTL-to-GDSII flow including synthesis, floorplanning, placement, CTS, routing, and sign-off for complex designs on 12nm and below technology nodes.
Role type
Senior IC physical design engineer
Builds
Semiconductor chips (MCUs, SoCs, Analog, power products)
Domain
Semiconductor / VLSI / Embedded Processing
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-GDSII implementation, Static Timing Analysis (STA), timing closure, EM/IR analysis, physical verification (LVS/DRC), floorplanning, placement, MultiTap-CTS, routing, Tcl scripting, Innovus, Genus, Primetime, Calibre
Preferred skills
DDR design knowledge
Technologies
Innovus, Genus, Primetime, Calibre
Responsibilities
Execute full RTL-to-GDSII flow; Perform Static Timing Analysis (STA) and ensure timing closure; Execute EM IR and physical verification checks; Collaborate with cross-functional teams; Handle complex designs on 12nm and below technology nodes
Seniority
Junior, hands-on IC