Mid Level ASIC Design Engineer
Core
Design and implement microarchitecture for high-performance, low-power AI ASICs integrating novel computational accelerators, compute, interconnects, and networking.
Role type
Mid-level ASIC Design Engineer
Builds
High-performance AI inference chips (ASICs)
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
RTL logic design (Verilog/System Verilog), IP integration (CPU into SoC), ARM/RISC-V/MIPS architectures, AMBA/APB/AXI protocols, ASIC front-end tools, low-power design (UPF), timing closure
Preferred skills
High-frequency timing closure, AI architecture knowledge (convolution, transformer)
Technologies
Verilog, System Verilog, UPF, AMBA, AXI, SPI, eMMC, I2C, GPIO
Responsibilities
Define and document microarchitecture, select and integrate 3rd-party IP blocks, collaborate with design verification and backend teams, run and analyze frontend synthesis, address synthesis issues, provide place-and-route guidance for timing closure
Seniority
Mid-level, hands-on IC
