Senior Hardware Design Engineer
Core
Design component units of the Reconfigurable Dataflow Unit (RDU) ASICs for AI workload acceleration systems.
Role type
Senior Hardware Design Engineer (ASIC)
Builds
Compute, memory, and networking subsystems for SambaNova's generative AI platform
Domain
AI hardware acceleration / ASIC design
Deliverable
production ML models
Required skills
SystemVerilog RTL design, computer architecture, digital logic design, PPA optimization, industry-standard interconnects (AXI, PCIe, Ethernet, HBM/DDR), digital logic synthesis, Static Timing Analysis (STA), SystemVerilog Assertions (SVA), EDA tool methodologies, Python scripting, Linux shell
Preferred skills
Full ASIC development cycle experience, AI workload acceleration techniques, low-power design (clock gating, DVFS), emulation or FPGA prototyping
Technologies
SystemVerilog, SVA, EDA tools, Python, Linux, Git
Responsibilities
Author microarchitecture specifications for compute, memory, or networking subsystems; Code, integrate, and debug SystemVerilog RTL for assigned blocks; Meet PPA targets using advanced digital design techniques; Partner with verification and physical design engineers to converge on functionality, timing, and area; Implement SVA and run lint, CDC, and LEC flows; Participate in design reviews; Support post-silicon bring-up and debug; Contribute to design flow improvements including AI and automation in EDA tool methodologies
Seniority
Senior, hands-on IC
