Principal RTL Design Engineer, IO & Memory Systems
Core
Design, integration, and implementation of high-speed IO and memory subsystems for the DataScale® platform to deliver reliable, high-performance AI systems at scale.
Role type
Principal RTL Design Engineer (IO & Memory Systems)
Builds
DataScale® platform (RDU-based AI inference hardware)
Domain
Semiconductor / AI Infrastructure / High-performance Computing
Deliverable
production ML models
Required skills
SystemVerilog RTL design, microarchitecture definition, ASIC design, protocol expertise (PCIe, Ethernet, CXL, HBM, AXI, APB), power/performance/area optimization, cross-functional triage, design flow management (lint, CDC/RDC, synthesis, timing constraints)
Preferred skills
End-to-end ASIC product delivery, emerging scale-up/scale-out protocols (ESUN, SUE, UAL, Ultra Ethernet), on-chip interconnect/traffic management (NoC, switches, arbiters), machine learning hardware accelerator architecture knowledge
Technologies
SystemVerilog, PCIe, Ethernet, CXL, HBM, AXI, APB, UCIe, NoC
Responsibilities
Engage in architecture exploration with system and chip architects; Drive feasibility studies and design trade-off analysis; Own microarchitecture definition and specification; Deliver synthesizable SystemVerilog RTL; Run front-end design flow end-to-end; Partner with STA and physical design teams; Collaborate with verification, emulation, software, and firmware teams; Improve design and integration methodology
Seniority
Principal, hands-on IC
