Senior Power Management IP Verification & Validation Engineer
Core
Verification and post-silicon validation of power management IP tightly coupled to the Reconfigurable Dataflow Unit (RDU) architecture for a full-stack generative AI platform.
Role type
Senior IC VLSI Power Management IP Verification & Validation Engineer
Builds
Bug-free power management systems for the SN40L chip, supporting low-power, high-performance rack system delivery.
Domain
Semiconductor / Generative AI Hardware Accelerators
Deliverable
production ML models
Required skills
SystemVerilog, UVM, SVA, C/C++, Python, shell scripting, pre-silicon verification, post-silicon validation, hardware debugging
Preferred skills
Power management domain knowledge, RDU architecture understanding, computer architecture fundamentals, AI-assisted workflow automation
Technologies
UVM, SVA, SystemVerilog, Python, C/C++, Shell
Responsibilities
Define and plan pre-silicon verification strategy; Execute pre-silicon verification of Power IPs to achieve high coverage; Lead functional and system-level validation of Power IPs post-silicon arrival.
Seniority
Senior, hands-on IC
