Principal DFT Engineer
Core
Design and implement DFT architecture, verification, and silicon bring-up for high-performance AI/ML RDU chips.
Role type
Principal Design for Test (DFT) Engineer
Builds
High-performance RDU chips for machine learning and artificial intelligence
Domain
Semiconductor hardware design, AI accelerators, SoC testing
Deliverable
production ML models | product features
Required skills
DFT architecture, ATPG, MBIST, JTAG, IEEE 1500, IEEE 1687/IJTAG, scan insertion, scan compression, hierarchical DFT, silicon diagnosis, failure localization, STA constraints for DFT, Verilog/System-Verilog simulation
Preferred skills
Siemens Tessent tool flow, cell-aware ATPG, low-power DFT, ATE pattern deployment, multi-die/chiplet DFT, known-good-die test, large compute SoC experience
Technologies
Siemens Tessent, Verilog, System-Verilog, IEEE 1500, IEEE 1687
Responsibilities
Define and implement block-level and SoC-level DFT architecture; Develop and maintain ATPG flows for stuck-at, at-speed, and advanced fault models; Develop automation for DFT insertion, ATPG, coverage analysis, and pattern generation; Maintain JTAG and IEEE 1500/1687 infrastructure; Generate production-quality ATPG and MBIST patterns; Collaborate with STA and Physical Design teams on timing closure; Support silicon diagnosis, failure localization, and yield analysis.
Seniority
Principal, hands-on IC
