Principal Design Verification Engineer
Core
Own end-to-end verification for a major subsystem of the RDU (reconfigurable dataflow silicon) for SambaNova's generative AI platform, ensuring quality and reliability before production.
Role type
Principal Design Verification Engineer (Senior IC)
Builds
Next-generation RDU chip for machine learning and AI systems
Domain
Semiconductor / AI Hardware Accelerators
Deliverable
production ML models
Required skills
SystemVerilog, SVA, UVM/OVM/VMM, Python, C/C++, ASIC design verification, coverage closure, testbench architecture, debug of hard failures, technical leadership, computer architecture, ML accelerators
Preferred skills
High-speed I/O verification (PCIe, Ethernet, HBM, DDR), performance verification, formal verification, third-party IP integration, emulation/FPGA prototyping, post-silicon bring-up, AI tools for verification
Technologies
SystemVerilog, Python, C/C++, UVM, OVM, VMM, FPGA, Emulation platforms
Responsibilities
Own test plan, testbench architecture, coverage model, and sign-off criteria for a major RDU subsystem; drive coverage closure ahead of tape-out; develop testbench components, agents, checkers, and stimulus; serve as technical authority for verification decisions and lead debug on hardest failures; own regression health and failure triage; advance DV methodology with reusable infrastructure and AI-assisted workflows; contribute to emulation/FPGA prototyping and silicon bring-up; mentor engineers to raise team verification practice
Seniority
Principal, hands-on IC with technical leadership
