Signal and Power Integrity Engineer
Core
Lead signal integrity (SI) and power integrity (PI) analysis and optimization for High-Performance Computing (HPC) leveraging advanced 2.5D/3D packaging technologies.
Role type
Senior IC Signal and Power Integrity Engineer
Builds
Custom silicon solutions for AI/ML hardware acceleration (TPU)
Domain
Semiconductor / High-Performance Computing / AI Hardware
Deliverable
production ML models
Required skills
SI/PI analysis and optimization, 2.5D/3D packaging technologies, chip floorplanning, power distribution networks (PDN), high-speed interface IPs, memory interfaces (IO PHY, SerDes), post-silicon validation, simulation methodologies, Python/MATLAB/C++
Preferred skills
Master's/PhD in EE/CS, SI/PI for HBMx/D2D/chiplets/PCIe, silicon interposers/bridges/3D die stacking
Technologies
HFSS, ADS, Sigrity, Siwave
Responsibilities
Lead SI/PI analysis and optimization for HPC; Partner early in product definition to influence floorplanning and PDN; Evaluate high-speed interface IPs; Drive post-silicon validation and qualification; Partner with silicon/system/vendor teams to develop simulation methodologies
Seniority
Senior, hands-on IC
