Staff Engineer Digital Verification and Methodology
Core
Drive verification excellence and scalable methodologies for complex IP, subsystem, and SoC developments, partnering with cross-functional teams to deliver robust, reusable verification solutions.
Role type
Staff Engineer, Digital Verification and Methodology
Builds
Reusable verification environments, Verification IP (VIP), and scalable verification methodologies for digital IP, subsystems, and SoCs.
Domain
Semiconductor / Hardware Design / Digital Verification
Required skills
SystemVerilog, UVM, constrained-random verification, formal verification, verification planning, coverage analysis, test generation, workflow automation, technical leadership, cross-functional collaboration
Preferred skills
AI-based verification methodologies, knowledge reuse, continuous improvement
Technologies
SystemVerilog, UVM, AI-based verification tools
Responsibilities
Define verification concepts, strategies, and measurable plans for digital IP, subsystems, and SoC projects; Develop and maintain SystemVerilog and UVM verification environments, reusable components, and Verification IP; Create verification specifications, test scenarios, assertions, coverage strategies, and closure criteria; Apply constrained-random, metric-driven, and formal verification techniques to validate complex designs; Lead methodology capabilities including roadmap definition, requirements, implementation, documentation, enablement, adoption, and continuous improvement; Evaluate and apply AI-based methodologies for verification planning, test generation, debug, coverage analysis, knowledge reuse, and workflow automation; Collaborate with concept, design, application engineering, and methodology teams to communicate technical direction, status, risks, and quality metrics.
