Staff Engineer Digital Functional Verification (f/m/div)
Core
Develop UVM-based verification environments and test scenarios for digital ICs using System Verilog, ensuring low-power verification and applying formal verification methods.
Role type
Staff Engineer, Digital Functional Verification
Builds
Innovative and high-quality semiconductor products (ICs)
Domain
Semiconductor / Digital IC Design
Required skills
UVM, System Verilog, Formal Verification, Constrained Random Verification, Verification Planning, Verification Tracking, Low-Power Verification (UPF), RTL Design, Mixed-Signal Verification
Preferred skills
Ethernet Protocols (Bridge, PHY, MACs), Cadence Verification Software, Technical Leadership, Project Management
Technologies
SystemVerilog, UVM, UPF, SVA, PSL, Cadence
Responsibilities
Design and develop verification environments for ICs using UVM; Implement test scenarios using System Verilog and Constrained Random Approach; Identify sub-modules suitable for specific verification methods (Simulation/Formal); Define verification methodology and plans; Collaborate with global development sites and business units; Contribute to internal knowledge exchange; Control verification management activities (planning, tracking, reporting).
Seniority
Staff, Technical Leadership
