Senior Staff Engineer - DFT
Core
Define, implement, verify, and debug DFT architecture for SoC/Full Chip designs, including scan insertion, BIST, and post-silicon debug.
Role type
Senior Staff IC DFT Engineer
Builds
Testable SoC designs and silicon debug solutions
Domain
Semiconductor / VLSI Design
Required skills
SoC DFT architecture, Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic, DRC analysis, ATPG, Memory BIST, JTAG/BSCAN/iJTAG, P1500, fault models (Stuck-at/TDF/Bridging/Cell-aware/iddq), Zero delay/SDF simulation, post-silicon debug, ASIC design flow
Preferred skills
LEC, CLP, power analysis, Perl/Tcl/Python scripting
Responsibilities
Define and implement SoC DFT architecture, perform ATPG and DRC analysis, implement and verify Memory BIST, manage JTAG/BSCAN/iJTAG and P1500, debug scan/MBIST/JTAG simulations, conduct post-silicon debug of yield fallout
Seniority
Senior Staff, hands-on IC
