Engineer / Senior Engineer Physical Design
Core
Physical Design Engineer responsible for chip implementation (Synthesis, Floorplanning, Place and Route, Clock Tree Synthesis, IP integration, Physical Verification) and Timing Sign-off checks.
Role type
Physical Design Engineer
Builds
Integrated circuit layouts and timing-verified netlists for semiconductor chips
Domain
Semiconductor / VLSI Design
Required skills
Physical Design Implementation, Floorplanning, Place and Route, Clock Tree Synthesis, Physical Verification, Timing Sign-off, Static Timing Analysis, Scripting (Tcl, Python, Perl, Shell), IREM flow, Low power design
Preferred skills
Low power design, Automation scripting
Technologies
FusionCompiler, EDA tool chain, Tcl/tk, Python, Shell, Perl, Make flow
Responsibilities
Execute Physical Design Implementation or Timing Checks, Plan and execute layout development to meet project milestones, Automate design work using scripting languages
Seniority
Junior to Mid-level (0-4 years experience)
