Senior Staff Engineer Verification (f/m/div)
Core
Create and define verification plans for digital verification of Mixed Signal designs, execute tests on RTL and gate-level, and debug issues in design and verification environments.
Role type
Senior Staff Engineer Verification (Mixed Signal)
Builds
Digital verification environments for Mixed Signal designs
Domain
Semiconductor / Hardware Design
Required skills
SystemVerilog, UVM, Constrained Random Verification, RTL design, Mixed Signal circuits, Debugging, Leadership, Mentoring
Preferred skills
Python, GIT, Analog design knowledge
Technologies
Xcelium, Verdi, vManager, SystemVerilog, UVM
Responsibilities
Create and define verification plans for Mixed Signal designs; Create and improve verification environments using SystemVerilog/UVM; Execute tests and debug issues in RTL and gate-level; Lead and coordinate verification engineers; Mentor junior colleagues; Contribute to enhancement of methodologies and flows.
