Senior / Staff Engineer - Mixed Signal Verification
Core
Senior verification engineer developing and executing pre-silicon verification plans for complex mixed-signal and digital semiconductor projects.
Role type
Senior IC verification engineer (mixed-signal/digital)
Builds
Verification environments, test cases, and metrics for RTL IP and sub-systems
Domain
Semiconductor / Mixed-signal IC design
Required skills
UVM methodology, SystemVerilog, VHDL, Verilog, C, C++, RTL design, verification environment creation, test case development, simulation performance optimization, cross-domain verification coordination
Preferred skills
AMS verification tools (XA/VCS, AMS-Designer), ISO26262 automotive standards, requirements management, technical mentoring
Technologies
UVM, SystemVerilog, VHDL, Verilog, C, C++, XA/VCS, AMS-Designer
Responsibilities
Define and review verification plans, develop test cases and metrics, create reusable verification components, coordinate verification activities across projects, identify and fix methodology deficiencies, bridge pre-silicon verification and post-silicon validation, mentor junior engineers
Seniority
Senior, hands-on IC with technical lead responsibilities
