Senior Staff Engineer
Core
VLSI Design Engineer responsible for synthesis execution, timing closure, and low-power sign-off for complex SoCs targeting IoT and MCU markets.
Role type
Senior Staff VLSI Design Engineer (Synthesis & Low-Power)
Builds
Complex low-power System-on-Chips (SoCs) for IoT and Microcontroller Unit (MCU) markets
Domain
Semiconductor / VLSI Design / Low-Power Design
Required skills
Synthesis, Logic Equivalence Checks (LEC), UPF-based Low-Power Sign-off, Timing Analysis, Constraints Development, Advanced Node Technologies (40nm/28nm/22nm), Shell Scripting, Perl Scripting, TCL Scripting
Preferred skills
Cross-functional collaboration, Problem-solving, Design closure
Technologies
Synthesis tools, LEC tools, UPF, Shell, Perl, TCL
Responsibilities
Responsible for synthesis execution, timing closure, and low-power sign-off for complex low-power SoCs; Owned synthesis implementation and timing convergence activities at both pre-DFT and post-DFT stages; Conducted low-power Logic Equivalence Checks (LEC) across RTL-to-Netlist and Netlist-to-Netlist stages; Led UPF-based low-power verification and sign-off across synthesis, post-layout, and other stages.
