Principal Engineer
Core
Lead and drive verification of complex semiconductor designs, defining strategies and developing scalable constraint-random verification environments for IPs, subsystems, and SoCs.
Role type
Principal SoC/IP Verification Engineer
Builds
Verification environments and strategies for semiconductor IPs, subsystems, and SoCs
Domain
Semiconductor / Hardware Verification
Required skills
System Verilog, UVM, constraint-random verification, verification architecture, verification closure, functional verification, power-aware verification, gate-level verification
Responsibilities
Lead and contribute to the definition of verification architecture and strategy for IPs, subsystems, and SoCs; Develop robust constraint-random verification environments from scratch using SystemVerilog
