Senior Engineer Verification
Core
Develop SystemVerilog RNM models and verification flows for analog/mixed-signal blocks within SoC-level power management ICs.
Role type
Senior IC verification engineer (analog/mixed-signal)
Builds
Power management ICs (Multi-phase controllers, power switches, ADC, buck-boost controllers, LDO)
Domain
Semiconductor / Power Systems
Required skills
SystemVerilog, UVM, Analog design concepts, EDA tools (Cadence Virtuoso, Xcelium, APS/XPS), Scripting (Shell/Perl/Python), AMS methodologies
Preferred skills
None stated
Technologies
Cadence Virtuoso, Xcelium, APS/XPS, DMS verification flow
