Senior Staff Engineer Digital Design
Core
Physical Design and Timing Closure of complex, low power SoCs for IoT and MCU markets.
Role type
Senior Staff Engineer, Physical Design
Builds
Hierarchical blocks and top-level SoCs
Domain
Semiconductor / VLSI Design
Required skills
Physical design, Timing closure, Floor planning, IO planning, Package co-design, Power grid design, Place and route, Clock tree synthesis, Timing closure, Static/Dynamic IR drop, Physical verification, Low power techniques, Multi-voltage island design, Scripting (Shell, Perl, Tcl), Make flow
Preferred skills
Understanding of 40nm/28nm/22nm technologies, QoR improvement methodologies
Technologies
Industry standard tools for physical design and signoff
Responsibilities
Drive die area, performance, and power goals; Execute physical design implementation stages; Optimize flow/methodology for Quality of Result (QoR); Coordinate with colleagues and share expertise.
Seniority
Senior Staff, hands-on IC
