Senior Verification Engineer (f/m/div)
Core
Develop comprehensive verification definitions, methodologies, and behavioral models for analog/mixed-signal blocks to validate chip-level specifications and designs.
Role type
Senior IC verification engineer (ASIC/SoC)
Builds
Digital ASIC chips and SoCs for power systems and IoT
Domain
Semiconductor / Hardware Design
Required skills
UVM-based verification, coverage-based verification, analog/mixed-signal behavioral modeling, digital ASIC verification, specification analysis, documentation
Preferred skills
Experience in direct testing and random testing, IP-level verification
Technologies
UVM, SystemVerilog (implied by UVM/ASIC context), analog behavioral modeling tools
Responsibilities
Develop comprehensive verification definitions and methodologies for a variety of products, Participate in chip-level coverage-based verification activities, Analyze and review product specifications to build and execute robust verification plans, Generate behavioral models for analog blocks and integrate them into the verification cycle, Create and maintain proper documentation for all verification tasks, plans, and related workflows
Seniority
Junior to Mid-level (0-3 years experience)
