SoC High-Speed Interface Architect
Core
Own the SoC-level integration architecture for high-speed interface PHYs on next-generation automotive microcontrollers, defining placement, power delivery, and electrical compliance.
Role type
SoC High-Speed Interface Architect
Builds
Chip-level integration architecture for automotive microcontroller platforms
Domain
Automotive semiconductor / SoC architecture
Required skills
SoC architecture, high-speed interface PHY integration, signal integrity analysis, power delivery design, electrical compliance, floorplanning, technical documentation (ISO 26262)
Technologies
LPDDR, Ethernet PHY, HSPHY
Responsibilities
Define placement strategy and electrical constraints for high-speed PHYs; Maintain chip-level interface specifications for PHY IP teams; Serve as primary interface to PHY IP teams and external vendors; Perform or oversee early signal integrity simulation and parasitic analysis; Review and sign off on PHY IP integration results and floorplan proposals; Maintain technical architecture documentation per ISO 26262; Drive datasheet content for high-speed interface parameters
Seniority
Mid-to-Senior, hands-on IC
