MEMS Analog Mixed Signal Verification SR/Team Leader
Core
Mixed Signal verification engineer developing test benches, verification components, and test cases for analog, digital, and mixed-signal ASIC simulations from specification to industrialization.
Role type
Senior IC mixed-signal verification engineer (team leader)
Builds
ASIC verification environments and test cases for MEMS analog mixed-signal chips
Domain
Semiconductor / Analog Mixed-Signal Design
Required skills
Analog custom circuit design (ADC, DAC, comparators), Analog/digital/mixed-signal simulation, SystemVerilog Assertions, Bugs analysis and reporting, Subsystem and SoC level verification methodologies
Preferred skills
SystemVerilog and UVM methodology, Verilog-AMS, Python scripting, UPF for mixed-signal simulations, Communication protocols (I2C, SPI, I3C), Formal tools, Version control systems
Technologies
Cadence, SystemVerilog, UVM, Verilog-AMS, Python, UPF, I2C, SPI, I3C
Responsibilities
Define and develop verification test benches, develop verification components, create simulation test cases, debug failures, work on cutting-edge verification methodologies at Subsystem and SoC levels
Seniority
Senior, hands-on IC with team leadership potential
