Principal CAD RTL Methodology and Design Engineer
Core
Define and lead RTL design methodology, static signoff flows, and AI-assisted design for Ericsson's 5G/6G ASIC and FPGA programs.
Role type
Principal CAD RTL Methodology and Design Engineer
Builds
Vendor-agnostic static signoff flows, reusable RTL frameworks, and AI-integrated design tools for advanced nodes (Intel 18A, TSMC 3/2nm).
Domain
Semiconductor / ASIC & FPGA Design
Required skills
SystemVerilog/Verilog RTL design, Static signoff (CDC/RDC), Python scripting, CI/CD automation, Lint rule architecture, AI tool integration (ChipAgents/Kiro), Low-power design (UPF), Microarchitecture.
Preferred skills
EDA tool expertise (Synopsys VC SpyGlass, Cadence JasperGold), OneRun platform experience, Register generation tool strategy.
Technologies
SystemVerilog, Verilog, Python, Linux, Jenkins, OneRun, Synopsys VC SpyGlass, Cadence JasperGold, ChipAgents, Kiro, Intel 18A, TSMC 3nm/2nm.
Responsibilities
Define coding guidelines, lint rules, and signoff criteria; Architect structural and formal CDC/RDC flows; Build vendor-agnostic static signoff flows; Drive RTL reuse via configurable frameworks; Apply AI tools for RTL development and triage; Strengthen FE–BE handoff checks.
Seniority
Principal, hands-on IC with technical leadership
