Director of 3D Stacked Logic Design
Core
Lead design and implementation of high-speed digital IP for 3D-stacked DRAM peripheral circuits and DFT, driving co-development with U.S. customers for DRAM-on-Logic systems.
Role type
Director of 3D Stacked Logic Design
Builds
High-speed digital IP for 3D-stacked DRAM peripheral circuits and DFT
Domain
Semiconductor / Memory / 3D-Stacked DRAM
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design and implementation, memory PHY design, hard macro IP for high-speed circuits, memory controller design, memory BIST, DRAM DFT/DFD, PPA analysis and optimization, physical design
Preferred skills
Co-design of 3D-stacked DRAM logic dies, foundry verification of service-ready IPs, IP business infrastructure setup
Technologies
Verilog, VHDL
Responsibilities
Lead design of high-speed digital IP for 3D-stacked DRAM peripheral circuits and DFT with U.S.-based customers; Drive foundry verification of service-ready IPs and infrastructure setup for IP business; Deliver services to ensure seamless IP integration in customer design environments; Strengthen leadership in the DRAM-on-Logic era through advanced digital IP design; Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations; Co-design of 3D-stacked DRAM logic die with U.S.-based customers
Seniority
Director, strategic leadership & hands-on IC